The invention is directed to an improved approach for designing, analyzing, and manufacturing integrated circuits.
An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system can be used to take the high level behavior descriptions of the IC device and to generate one or more netlists for the electronic design. A netlist describes, for example, interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections. After an integrated circuit designer has created the physical design of the circuit, the integrated circuit designer then verifies and optimizes the design using a set of EDA testing and analysis tools.
Circuit designs may include digital circuitry, analog circuitry, or a combination of both analog and digital portions. Specialized tools often need to be used to perform verification tasks for each of these types of circuits. For example, verification of digital circuit designs is often performed by EDA tools that are specifically configured to operate upon digital designs.
The issue addressed by the present disclosure is that analog verification does not have formalized methods, tools and flows that, for digital verification, have evolved over many years. It is not possible to apply the digital verification methods to the analog problem as the analog and digital verification problem are fundamentally different in the details.
One approach that has been taken to verify analog circuits is to use cellviews. A cellview is a basic unit of design data represented as a file in a library. The cellview can be created to include any number of tests which reference that cell and/or other cells. An example approach to implement cellviews is provided by an analog design environment, which provides capabilities to explore, analyze, and verify a design against the user's desired goals.
Conventionally, cellviews are used in a self-contained approach for verification, where individual cellviews are used in distinct analog islands within the overall design. The drawback with this approach is that it cannot be easily adopted for other and more complex verification purposes (e.g., ones that extend beyond the self-contained capabilities within the individual cellview). This means that the analog aspects of a complete verification plan (e.g., SoC (system on chip) verification plan) cannot be connected into the cellviews of analog design environments. As a result, it is not possible with conventional tools to obtain a complete picture of the dynamic or final status of verification of all of the blocks within the design.
With conventional tools, the analog parts of the design are often verified in an ad-hoc manner based on the potentially limited information available to, and the skills of, the analog designer. The analog design, the designer, and the test benches that are used to simulate the design, are trapped in analog islands within the digitally verified SoC. For complex verification tasks it is essential that the verification goal and requirements are predefined in a formalized manner. These drawbacks severely limit the scalability and flexibility for performing analog verification when using cellviews.
Therefore, it is clear that there is a need for an improved approach to perform verification of analog circuit designs.